//------------------------------------------------
// top.v
//
// James Forrest, 2013
// Based on code by:
// David_Harris@hmc.edu 9 November 2005
//
// Top level system including MIPS pipelined
// processor and external data and instruction
// memories
//------------------------------------------------

module TopMips(/*input         clk, reset,
               input  [15:0] interrupts,
               output [31:0] memAddr,
               inout  [31:0] memData,
               output  [3:0] memByteEn,
               output        memReadWriteBit,
               output        memEn,
               input         memDone*/
               input        clk, reset,
               output [6:0] seg,
               output       dp,
               output [3:0] an,
               input  [3:0] btn,
               input  [7:0] sw,
               output [7:0] led
               );

    wire [31:0] pcF, instrF, dataAddrM, readDataM, writeDataM, debugData;
    wire instrAckF, dataAckM, dataReadM;
    wire [4:0] debugAddress;

    // use the debug register stuff! hook up register 27 to on board peripherals
    // allows test programs to set the values that will be returned
    assign debugAddress = 5'd27;
    assign debugData = {seg, dp, an, btn, sw, led};

    // wire the buttons as interrupts, just because
    wire [15:0] interrupts = {12'd0, btn};

    // this module is not used in synthesis, only for simulation as the device under test
    mips   mips(clk, reset, pcF, instrF, 1'b1, 1'b0, dataWriteM, dataReadM, 1'b1, 1'b0, dataAddrM, writeDataM, readDataM, interrupts, debugAddress, debugData);
    imem   imem(pcF[31:2], instrF);
    dmem   dmem(clk, dataWriteM, dataAddrM, writeDataM, readDataM);

	// instantiate processor and memories
    /*mips   mips(clk, reset, pcF, instrF, instrAckF,
           dataWriteM, dataReadM, dataAckM, dataAddrM, writeDataM, readDataM,
           debugAddress, debugData);
    memsys memsys(clk, reset, pcF[31:2], instrF, 1'b1, instrAckF,
           dataAddrM, writeDataM, 4'b1111, readDataM, dataWriteM, dataReadM, dataAckM,
           1'b0,
           memAddr, memData, memByteEn, memReadWriteBit, memEn, memDone);*/

endmodule
